Glass PCB
The engineer's reference for circuit boards on glass — substrate materials, design rules, through-glass vias, manufacturing flow, cost models and live calculators. Built for PCB designers evaluating glass against FR-4 and ceramics.
What is a Glass PCB?
A glass PCB is a printed circuit board built on a glass substrate — borosilicate, fused silica, soda-lime or sapphire — instead of woven-glass epoxy laminate. Conductors are formed by thin-film metallization: a sputtered Ti/Cu seed layer is patterned by photolithography and electroplated to 5–20 µm of copper. The result is an optically flat, transparent, hermetic board with surface roughness below 1 nm Ra — about 400× smoother than low-profile FR-4 copper.
That smoothness and the tight dielectric tolerance (Dk held to ±1–2 % across a panel) are why glass substrates dominate emerging mmWave packaging, antenna-in-package, photonics and high-density interposer work. Through-glass vias (TGV) connect both sides at 30–100 µm diameters, a density FR-4 mechanical drilling cannot reach.
The trade-offs are real: glass is brittle, thermally insulating (~1 W/m·K) and costs more to process. This page gives you the material data, design rules and cost models to decide where it wins. For full fabrication capabilities, stackups and quoting, see the Glass PCB manufacturing service at PCBSync.
Glass PCB Materials
Four substrate families cover nearly every glass PCB design. Select a card to highlight its column in the property table below.
| Property | Borosilicate | Fused silica | Soda-lime | Sapphire |
|---|---|---|---|---|
| Dk (1 MHz – 10 GHz) | 4.6 | 3.8 | 7.2 | 9.4 – 11.5 |
| Loss tangent @ 10 GHz | 0.004 | 0.0002 | ≈ 0.01 | 0.00005 |
| CTE (ppm/K) | 3.25 | 0.55 | 8.6 | 5.3 – 7.0 |
| Thermal cond. (W/m·K) | 1.2 | 1.4 | 1.0 | 27 – 35 |
| Max operating temp | ≈ 450 °C | ≈ 1000 °C | ≈ 350 °C | > 1000 °C |
| Transmittance (visible) | 92 % | 93 % (UV–IR) | 90 % | 86 % |
| Relative cost index | 1.6× | 3.5× | 1.0× | 8 – 10× |
| Typical thickness (mm) | 0.1 – 1.1 | 0.2 – 1.0 | 0.4 – 1.1 | 0.3 – 0.7 |
| Representative datasheet values at 25 °C (Schott BOROFLOAT® 33 / D263, Corning HPFS®, generic float glass, c-plane sapphire). Loss tangent rises with frequency — verify against your band. Sapphire Dk is anisotropic (⊥/∥ c-axis). | ||||
Glass PCB Engineering Tools
Three live calculators tuned to glass substrates. All run locally in your browser — nothing is uploaded.
T-01Substrate Selector
Answer three questions, get a recommended glass with reasoning.
T-02Microstrip Impedance on Glass
Hammerstad–Jensen Z₀ for a single-ended trace over a back-side ground plane.
T-03Cost Estimator
Budgetary 2026 pricing for prototype-to-volume glass PCB fabrication.
Glass PCB Design Tips
Glass rewards clean layout and punishes stress concentration. Six rules that prevent 90 % of first-spin failures.
Respect the brittle edge
Keep copper, pads and TGVs ≥ 0.5 mm from board edges and ≥ 2×Ø between via walls. Edge chips from singulation become crack initiators under any copper stress.
Round every corner
No sharp internal corners in the board outline — minimum internal radius R ≥ 0.5 mm, external R ≥ 0.3 mm. Slots and cutouts need generous fillets; a square notch halves flexural strength.
Design joints for CTE mismatch
Glass sits at 0.55–8.6 ppm/K vs ~21 ppm/K for SAC solder. Keep packages ≤ 10 mm on low-CTE glass, avoid large thermal paddles on soda-lime, and underfill BGAs/QFNs that must survive −40…+125 °C cycling.
Spec TGVs the fab can drill
Safe baseline: Ø 80 µm at ≥ 200 µm pitch, aspect ratio ≤ 10:1. LIDE processes reach Ø 30 µm in 0.3 mm glass. Always pad TGVs with annular ring ≥ 25 µm per side.
Spread heat in copper, not glass
Glass conducts ~1 W/m·K — 100× worse than alumina. Pour thick copper (15–20 µm) under hot parts, stitch thermal TGVs to a back-side spreader, or pick sapphire when dissipating > 1 W/cm².
Plan singulation early
No V-score, no mouse bites — glass is cut by laser or dicing saw only. Leave ≥ 3 mm panel rails, add fiducials on the rail, and keep the dicing street ≥ 0.3 mm clear of copper.
How a Glass PCB Is Manufactured
Glass boards are built with thin-film and panel-level packaging processes, not laminate pressing. The sequence below is the standard double-sided TGV flow.
Substrate prep
Float or down-draw glass panels are cut, edge-ground and cleaned (RCA / plasma) to particle-free, < 1 nm Ra surfaces.
TGV formation
Laser-induced deep etching (LIDE) or laser drilling + HF etch opens 30–100 µm through-glass vias with crack-free walls.
Seed metallization
Sputtered Ti/Cu (≈ 50/200 nm) coats both faces and via walls, giving adhesion the copper plating will build on.
Photolithography
Dry-film or spray resist is exposed by laser direct imaging — 10 µm lines are routine, < 5 µm with semi-additive plating.
Copper electroplating
Pattern plating grows traces and via fill to 5–20 µm. Pulse plating keeps TGV fill void-free at 10:1 aspect ratios.
Etch & strip
Resist strip and flash seed etch isolate the circuit. The smooth glass interface leaves near-vertical conductor sidewalls.
Surface finish
ENIG or ENEPIG over copper enables SAC reflow and Au wire bonding; OSP serves cost-driven single-side builds.
Singulation & test
Laser cutting or dicing saw separates boards; AOI plus flying-probe electrical test close out the lot.
Glass PCB Cost
Glass boards price like thin-film parts, not laminate. Five drivers set most of the quote — get them right and the estimator above lands within a sensible band.
Substrate material & area
Cost scales with cm². Soda-lime is the floor; fused silica ≈ 3.5×, sapphire ≈ 8–10×.
TGV count & geometry
Laser via formation is serial. Thousands of vias, small diameters or 10:1 ratios add machine hours.
Line width & layer count
10 µm lithography needs cleaner rooms and better yield management than 100 µm; each metal layer repeats the full thin-film loop.
Quantity & panel utilization
NRE (masks, fixtures) amortizes fast. Filling a 510 × 515 mm panel drops per-board cost 3–5× vs prototypes.
Finish & tolerances
ENEPIG, ±10 µm outline tolerance or hermetic sealing each add inspection and process steps.
Where Glass PCBs Win
Pick glass when smoothness, stability, transparency or via density is the bottleneck — these six fields already do.
mmWave & Antenna-in-Package
Sub-nm conductor roughness and ±1 % Dk hold antenna gain and filter response stable from 24 to 110 GHz.
5G/6G FR2 · radar · phased arraysPhotonics & Co-Packaged Optics
Route light through the substrate itself: ion-exchanged waveguides, fiber V-grooves and lasers share one glass carrier.
Optical engines · LiDAR · AR combinersSemiconductor Interposers & Test
CTE matched to silicon and 30 µm TGVs make glass the 2.5D interposer and probe-card substrate of record.
Chiplets · panel-level packagingBiosensors & Microfluidics
Chemically inert, optically clear and anodic-bondable — electrodes, channels and optics integrate on one chip.
Lab-on-chip · PoC diagnosticsTransparent Electronics & Displays
Copper-on-glass drives microLED panels, smart windows and HUDs where the circuit must disappear into the optics.
microLED · automotive HUDHarsh-Environment Sensing
Hermetic, moisture-proof and stable past 450 °C, glass and sapphire boards survive where FR-4 delaminates.
Downhole · aerospace · EV powerGlass PCB — Frequently Asked Questions
A printed circuit board built on a glass substrate — borosilicate, fused silica, soda-lime or sapphire — instead of FR-4 laminate. Copper conductors are sputtered and electroplated onto the glass, producing very smooth, fine-line circuits on a flat, transparent, dimensionally stable dielectric.
Prototypes run roughly 5–20× equivalent FR-4: a 50 × 50 mm double-sided borosilicate board is about $45–$120 each at 10 pieces plus $300–$700 tooling. At panel-level volume on soda-lime glass, per-board cost can fall below $5. Use the T-03 estimator above for your geometry.
Yes — standard SAC305 reflow works on ENIG or ENEPIG pads, as the photo at the top of this page shows. Because glass CTE (0.55–8.6 ppm/K) is far below solder and component bodies, large packages and big thermal pads need CTE-aware land patterns, compliant joints or underfill for −40…+125 °C cycling.
Through-glass vias (TGVs) are formed by laser-induced deep etching (LIDE) or laser drilling followed by HF etching, then metallized with a sputtered seed layer and copper electroplating. Typical diameters are 30–100 µm at pitches down to 150 µm, with aspect ratios to about 10:1.
Thin-film photolithography routinely delivers 10–50 µm line/space, and semi-additive processes reach below 5 µm. Printed or laser-structured conductors are coarser at 75–150 µm. The sub-nm glass surface keeps conductor edge roughness — and therefore RF loss — exceptionally low.
No. ITO glass carries a transparent conductive oxide at 10–100 Ω/sq for displays and touch panels. A glass PCB uses real electroplated copper (µΩ·cm) that carries amps and accepts soldered components. Transparent-electronics designs often combine both on one substrate.
Ready to build on glass?
Send your stackup, via map and Gerbers for a manufacturability review and firm quote — borosilicate, fused silica, soda-lime and sapphire, prototype to panel-level volume.
Get a Glass PCB quote →